Interposer and manufacturing method thereof

ABSTRACT

A manufacturing method of an interposer for disposing a semiconductor chip and an external terminal at two opposing sides includes the following steps. An active device is bonded to a first redistribution structure, wherein an active surface of the active device is in electrical contact with the first redistribution structure. A dielectric layer is formed on the first redistribution structure to encapsulate the active device. A second redistribution structure is formed over the dielectric layer to be electrically coupled to the first redistribution structure, wherein the first conductive pattern of the first redistribution structure is formed according to a first design rule to be finer than a second conductive pattern of the second redistribution structure formed according to a second design rule, the semiconductor chip and the external terminal are configured to be respectively disposed on the first conductive pattern and the second conductive pattern.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No. 16/505,734, filed on Jul. 9, 2019, now pending, which claims the priority benefit of U.S. provisional application Ser. No. 62/711,628, filed on Jul. 30, 2018. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to an interposer, and more specifically relates to an interposer with an active device embedded therein.

2. Description of Related Art

As the electronic industry has rapidly developed, the trend in semiconductor dies has been to gradually move toward miniaturization with improved functions. The terminal pitch of the semiconductor die has become narrower, whereas the degree to which a printed circuit board for the semiconductor die mounted thereon can have a fine pitch is limited. Thus, technologies for connecting the semiconductor die with the printed circuit board using an interposer having high-density interconnections have been developed. However, in order to meet the demand for greater integration with multi-functionality, various integrated circuit devices may take up significant space on the semiconductor die. Accordingly, fabricating an interposer that has active devices and high-density interconnections for communicating with and bonding to semiconductor chips while keeping the manufacturing process simple has become a challenge to researchers in the field.

SUMMARY OF THE INVENTION

The invention provides an interposer and a manufacturing method thereof. The interposer configured to connect a semiconductor chip to a circuit board includes an active device embedded therein to provide various functions.

The invention provides an interposer for disposing a semiconductor chip and an external terminal at two opposing sides. The interposer includes a first redistribution structure, a second redistribution structure disposed over and electrically coupled to the first redistribution structure, and an active device interposed between the first redistribution structure and the second redistribution structure. The semiconductor chip is disposed on and electrically connected to the first redistribution structure. A dimension of a first conductive pattern of the first redistribution structure is less than that of a second conductive pattern of the second redistribution structure, and the external terminal is disposed on and electrically connected to the second redistribution structure. An active surface of the active device is in contact with the first redistribution structure, and the active device is electrically coupled to the second redistribution structure through the first redistribution structure.

In some embodiments, the first redistribution structure includes a first conductive via connected to the first conductive pattern and tapered in a direction from the active device towards the external terminal, and the second redistribution structure includes a second conductive via connected to the second conductive pattern and tapered in a direction from the semiconductor chip towards the active device, wherein a dimension of the second conductive via is greater than that of the first conductive via. In some embodiments, the active device includes a router circuit disposed therein to be in electrical communication with the semiconductor chip. In some embodiments, a sidewall of the active device is connected to the active surface of the active device, and a portion of the second conductive pattern of the second redistribution structure extends along the sidewall of the active device to be in contact with the first conductive pattern of the first redistribution structure. In some embodiments, the active device includes a plurality of conductive terminals distributed at the active surface and connected to the first conductive pattern of the first redistribution structure. In some embodiments, the active device includes a rear surface opposite to the active surface, and a through semiconductor via extending from the active surface to the rear surface. In some embodiments, the active device is free of bump at the active surface, and an interface between the active surface of the active device and a surface of the first redistribution structure is free of solder material. In some embodiments, the interposer further includes an intermediate dielectric layer interposed between the first redistribution structure and the second redistribution structure, the active device is embedded in the intermediate dielectric layer, and the intermediate dielectric layer is thicker than the first redistribution structure. In some embodiments, the interposer further includes a third redistribution structure interposed between the intermediate dielectric layer and the second redistribution structure, a dimension of a third conductive pattern of the third redistribution structure is less than that of the second conductive pattern of the second redistribution structure, and a thickness of the third redistribution structure is thinner than the intermediate dielectric layer. In some embodiments, the interposer further includes a conductive through via penetrating through the intermediate dielectric layer and electrically coupled to the first redistribution structure and the third redistribution structure.

The invention further provides a manufacturing method of an interposer for disposing a semiconductor chip and an external terminal at two opposing sides. The method includes at least the following steps. An active device is bonded to a first redistribution structure, wherein an active surface of the active device is in electrical contact with the first redistribution structure. A dielectric layer is formed on the first redistribution structure to encapsulate the active device. A second redistribution structure is formed over the dielectric layer to be electrically coupled to the first redistribution structure, wherein the first conductive pattern of the first redistribution structure is formed according to a first design rule to be finer than a second conductive pattern of the second redistribution structure formed according to a second design rule, the semiconductor chip and the external terminal are configured to be respectively disposed on the first conductive pattern and the second conductive pattern.

In some embodiments, the second redistribution structure is formed by a build-up process. In some embodiments, a portion of the dielectric layer aside the active device is removed to form a through hole exposing at least a portion of the first conductive pattern of the first redistribution structure, and a conductive material is formed in the through hole to be in contact with the first conductive pattern of the first redistribution structure. In some embodiments, the through hole is tapered towards the first redistribution structure, the conductive material is formed inside the through hole and on a top surface of the dielectric layer, and then the conductive material on the top surface of the dielectric layer is patterned to form the second conductive pattern of the second redistribution structure. In some embodiments, the conductive material is formed inside the through hole to form a conductive through via, and then a third redistribution structure is formed on the conductive through via and the dielectric layer and a third conductive pattern of the third redistribution structure is formed according to the first design rule. In some embodiments, the active device is provided with a through semiconductor via formed therein, and a conductive connector is formed on a rear surface of the active device to connect the through semiconductor via. In some embodiments, before forming the third redistribution structure, a planarization process is performed on the conductive through via and the conductive connector. In some embodiments, the active device is bonded to the first conductive pattern of the first redistribution structure using a flip-chip process. In some embodiments, the active device is bonded to the first conductive pattern of the first redistribution structure using a direct copper-to-copper bonding process. In some embodiments, the first redistribution structure is formed on a temporary carrier, and the temporary carrier is de-bonded after forming the second redistribution structure to expose the first conductive pattern, and then the semiconductor chip is boned to a bond pad of the first conductive pattern of the first redistribution structure.

Based on the above, the interposer includes the first redistribution structure having the fine conductive pattern that can meet the requirements of high bump density of the semiconductor chips and the active device. The interposer includes the second redistribution structure having the coarser conductive pattern at the opposite side of the first redistribution structure for connecting the external terminals. In addition, the interposer includes the active device embedded therein for communicating the semiconductor chips disposed on the interposer. Since the active device may take up significant space on the semiconductor chips, by disposing the active device inside the interposer may release the space for semiconductor chips, thereby saving space on the semiconductor chips. Moreover, the interposer may include various functions by embedding designed active device(s) therein. Furthermore, the active device is buried at the side of the interposer proximal to the semiconductor chips, which may keep a short signal length in order to minimize a noise between operations and to improve a signal performance.

To make the above features and advantages of the present invention more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1A to FIG. 1E are schematic cross-sectional views illustrating a manufacturing method of an interposer according to some embodiments of the invention.

FIG. 2 is a schematic cross-sectional view illustrating an assembly including an interposer according to some embodiments of the invention.

FIG. 3A and FIG. 3B are schematic cross-sectional views illustrating a manufacturing method of an assembly including an interposer according to some embodiments of the invention.

FIG. 4 is a schematic cross-sectional view illustrating an assembly including an interposer according to some embodiments of the invention.

FIG. 5 is a schematic cross-sectional view illustrating an assembly including an interposer according to some embodiments of the invention.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 1A to FIG. 1E are schematic cross-sectional views illustrating a manufacturing method of an interposer according to some embodiments of the invention. Referring to FIG. 1A, a first redistribution structure 110 is formed over a temporary carrier 50. The temporary carrier 50 may be made of glass, plastic, silicon, metal, or other suitable materials as long as the material is able to withstand the subsequent processes while carrying a structure formed thereon. In some embodiments, a release layer 51 (e.g., a light to heat conversion film, or other suitable de-bonding layer) may be applied on a top surface of the temporary carrier 50 to enhance the releasability of the first redistribution structure 110 from the temporary carrier 50 in a subsequent process.

In some embodiments, the first redistribution structure 110 including a fine conductive pattern FP, a fine dielectric layer FD, and a fine conductive via FV is formed over the temporary carrier 50. A material of the fine dielectric layer FD may include polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), inorganic dielectric material (e.g., silicon oxide, silicon nitride, or the like), or other suitable electrically insulating materials. Materials of the fine conductive pattern FP and the fine conductive via FV may include copper, gold, nickel, aluminium, platinum, tin, combinations thereof, an alloy thereof, or another suitable conductive material.

For example, the fine conductive pattern FP may be formed over the temporary carrier 50 using a deposition process, a lithography process and an etching process, or other suitable processes. The fine conductive pattern FP may be a patterned conductive layer with fine line/space routing. Next, the fine dielectric layer FD including a plurality of openings may be formed over the temporary carrier 50 to cover the fine conductive pattern FP using, for example, a coating process, a photolithography and an etching process, or other suitable processes. The openings of the fine dielectric layer FD may expose at least the portion of the fine conductive pattern FP for electrical connection. In other embodiments, the fine dielectric layer FD is formed before the formation of the fine conductive pattern FP. A conductive material may be formed inside the openings of the fine dielectric layer FD to form the fine conductive vias FV using suitable deposition process. The conductive material may also be formed on the top surface of fine dielectric layer FD, and then patterned to form another level of the fine conductive pattern FP. The abovementioned steps may be performed multiple times such that the fine conductive patterns FP and the fine dielectric layers FD are alternately stacked and the fine conductive vias FV are embedded in the fine dielectric layers FD. The fine conductive vias FV may be formed to be electrically and physically connected between the fine conductive patterns FP in different layers. In some embodiments, the first redistribution structure 110 is a stack of layers having fine line/space routing. It should be noted that the first redistribution structure shown in FIG. 1A is merely exemplary, more levels or less levels of the first redistribution structure may be formed as required by the circuit design.

The first redistribution structure 110 includes a top surface 110 t and a bottom surface 110 b opposite to each other, where the bottom surface 110 b faces towards the temporary carrier 50. The fine conductive pattern FP and the fine dielectric layer FD at the bottom surface 110 b of the first redistribution structure 110 may be substantially leveled. The fine conductive vias FV may be tapered towards the temporary carrier 50. For example, the fine conductive vias FV includes slanted sidewalls, and a width (or diameter) of each fine conductive via FV gradually increases in a direction from the bottom surface 110 b to the top surface 110 t. Alternatively, the fine conductive vias FV include vertical sidewalls with respective to the bottom surface 110 b. In some embodiments, the fine conductive pattern FP at the bottom surface 110 b of the first redistribution structure 110 includes a plurality of chip bonding pads BP1 for the subsequently mounted semiconductor chips. In other embodiments, the chip bonding pads are formed after removing the temporary carrier 50.

Referring to FIG. 1B, an active device 120 is disposed on the first redistribution structure 110. Throughout the description, the term “active device” may refer to a die or a chip having electrical functions that may contribute to the electrical operation of the resulting structure. In some embodiments, the active device 120 includes an active surface 120 a connected to the top surface 110 t of the first redistribution structure 110, a rear surface 120 r opposite to the active surface, and a sidewall 120 s connected to the active surface 120 a and the rear surface 120 r. For example, the active device 120 includes a plurality of conductive terminals 122 distributed at the active surface 120 a and connected to the fine conductive pattern FP of the first redistribution structure 110. For example, the active device 120 is disposed on the first redistribution structure 110 using a flip-chip process. As semiconductor structures become more advanced, the need for higher input/output density leads to a tighter bump pitch. In some embodiments, the conductive terminals 122 are fine-pitched and/or high-density conductive bumps, and the fine conductive pattern FP of the first redistribution structure 110 allows the fine-pitched conductive bumps connected thereto. Alternatively, the conductive terminals 122 are omitted as will be described later in other embodiments. In some embodiments, the active device 120 performs the functions of router, switch, hub, bridge, etc. For example, the active device 120 is a router chip and includes router circuits (not shown) disposed therein so that the active device 120 may be in electrical communication with the subsequently mounted semiconductor chip. In some embodiments, a plurality of active device 120 is disposed on the first redistribution structure 110 side by side. It should be noted that the number of the active device 120 shown in FIG. 1B is merely exemplary, which construes no limitation thereto.

Referring to FIG. 1C, an intermediate dielectric layer 130 is formed on the first redistribution structure 110 to encapsulate the active devices 120. The intermediate dielectric layer 130 may include Ajinomoto build-up film (ABF), molding compound, bismaleimide triazine (BT), or other electrically insulating materials. The intermediate dielectric layer 130 may include or may be rigid dielectric material for protecting the active devices 120 therein. In some embodiments, a dielectric material is formed on the top surface 110 t of the first redistribution structure 110 to encapsulate the active devices 120 using molding, laminating, coating, or other suitable deposition process. Subsequently, a portion of the dielectric material is removed to form the intermediate dielectric layer 130 with a plurality of openings OP using lithography and etching, drilling, or other suitable removing process. In some embodiments, the openings OP are arranged around the active device 120. At least a portion of the fine conductive pattern FP of the first redistribution structure 110 at the top surface 110 t may be exposed by the openings OP of the intermediate dielectric layer 130 for further electrical connection.

In some embodiments, the inner sidewalls of the intermediate dielectric layer 130, which define the openings OP, may be inclined. For example, the opening sizes of the openings OP are tapered toward the first redistribution structure 120. Alternatively, the inner sidewalls of the intermediate dielectric layer 130, which define the openings OP, may be vertical with respective to the top surface 110 t of the first redistribution structure 110. In some embodiments, the intermediate dielectric layer 130 is thick enough to cover the entirety of the rear surface 120 r of the active device 120. For example, a thickness T2 of the intermediate dielectric layer 130 is greater than a thickness of the active device 120, and may also be greater than a thickness T1 of the first redistribution structure 110. In some embodiments, the intermediate dielectric layer 130 laterally covers the conductive terminals 122 of the active device 120.

Referring to FIG. 1D, a second redistribution structure 140 is formed on the intermediate dielectric layer 130 to be electrically and physically connected to the first redistribution structure 110. The second redistribution structure 140 may include a coarse dielectric layer CD stacked on the intermediate dielectric layer 130, a coarse conductive via CV embedded in the openings OP of the intermediate dielectric layer 130, and a coarse conductive pattern CP formed on the coarse dielectric layer CD and connected to the conductive via CV. A material of the coarse dielectric layer CD may include Ajinomoto build-up film (ABF), prepreg, bismaleimide triazine (BT), or other suitable electrically insulating materials. The material of the coarse dielectric layer CD may be the same with or different from the material of the intermediate dielectric layer 130. Materials of the coarse conductive pattern CP and the coarse conductive via CV may include copper, gold, nickel, aluminium, platinum, tin, combinations thereof, an alloy thereof, or another suitable conductive material.

In an exemplary embodiment, a conductive material is formed on the intermediate dielectric layer 130 and also formed inside the openings OP to form the coarse conductive via CV, and then the conductive material formed on the intermediate dielectric layer 130 is patterned to form the coarse conductive pattern CP. The coarse conductive vias CV formed in the openings OP are laterally covered by the intermediate dielectric layer 130. For example, the coarse conductive vias CV are disposed aside the active device 120, and the coarse conductive vias CV are tapered toward the first redistribution structure 110 and extend through the intermediate dielectric layer 130 to be physically and electrically connected to the fine conductive pattern FP of the first redistribution structure 110. Subsequently, a dielectric material is formed and patterned on the intermediate dielectric layer 130 to form the coarse dielectric layer CD, and the openings (not shown) of the coarse dielectric layer CD may expose at least a portion of the underlying coarse conductive pattern CP for further electrical connection. Alternatively, the dielectric material is pre-patterned and laminated on the intermediate dielectric layer 130 to form the coarse dielectric layer CD. The abovementioned steps may be performed multiple times, such that the coarse conductive pattern CP and the coarse dielectric layer CD are alternately stacked, and the coarse conductive vias CV are embedded in the coarse dielectric layer CD and connected to the coarse conductive pattern CP and the underlying fine conductive pattern FP. The another level of the coarse conductive vias CV may be formed on the coarse conductive pattern CP and laterally covered by the coarse dielectric layer CD such that the coarse conductive vias CV may be electrically and physically connected between the coarse conductive pattern CP in different layers.

It should be noted that a four-level redistribution structure shown in FIG. 1D is merely exemplary, more levels or less levels of the second redistribution structure 140 are possible. The topmost level of the coarse conductive patterns CP are formed on the topmost level of the coarse dielectric layers CD, and the topmost level of the coarse conductive patterns CP may include terminal bonding pads for the subsequently mounted external terminals. In some embodiments, the terminal bonding pads are referred to as under-ball metallurgy (UBM) pads for ball mount.

In some embodiments, a build-up process is performed to form the second redistribution structure 140. For example, during the build-up process, portions of the conductive material and dielectric materials are selectively removed to expose portions of other conductive material underneath the removed portions. Removal of the portions of conductive material may be performed, for, example, using a subtractive process, an etching process, etc. Alternatively, an additive process may be used to deposit the desired portions of conductive materials, other techniques, such as a semi-additive process, may be employed. In some embodiments, the conductive structure interconnected in the intermediate dielectric layer 130 and the overlying second redistribution structure 140 is free of solder material connected therebetween. In some embodiments, the conductive structure interconnected in the intermediate dielectric layer 130 and the underlying redistribution structure 110 is free of solder material connected therebetween.

Continue to FIG. 1D, a thickness T3 of the coarse dielectric layer CD may be thicker than the thickness T2 of the intermediate dielectric layer 130. The second redistribution structure 140 may be more rigid than the first redistribution structure 110. In some embodiments, the second redistribution structure 140 is more rigid than the intermediate dielectric layer 130. The dimensions of the coarse conductive pattern CP and the coarse conductive vias CV may be greater than those of the fine conductive pattern FP and the fine conductive vias FV, respectively. For example, the coarse conductive pattern CP is coarser and thicker than the fine conductive pattern FP, and the coarse conductive vias CV is larger than the fine conductive vias FV. In some embodiments, the first redistribution structure 110 is fabricated according to IC design rule, and the wiring (e.g., the fine conductive pattern FP, the fine conductive vias FV) are formed in fine pitch. The second redistribution structure 140 may be fabricated according to PCB design rule, and the wiring (e.g., the coarse conductive pattern CP, the coarse conductive vias CV) are formed in a larger scale compared to the wiring in the first redistribution structure 110. The design rules include width rule, spacing rule, enclosure rule, etc. For example, the minimum width of any shape in the IC design is much less than the minimum width of any shape in the PCB design. In some embodiments, the line width of the fine conductive pattern FP of the first redistribution structure 110 is less than that of the coarse conductive pattern CP of the second redistribution structure 140. The line/spacing (L/S) of the fine conductive pattern FP of the first redistribution structure 110 may be finer than that of the coarse conductive pattern CP of the second redistribution structure 140.

Referring to FIG. 1E, the temporary carrier 50 is removed. In some embodiments, a surface finishing layer 150 is formed on the topmost level of the second redistribution structure 140 before or after removing the temporary carrier 50. In some embodiments, after removing the temporary carrier 50, the surface finishing layer 150 is formed on the second redistribution structure 140 and also formed on the outermost levels of the first redistribution structure 110. For example, the temporary carrier 50 may be removed from the bottom surface 110 b of the first redistribution structure 110 by applying external energy between the bottom surface 110 b and the temporary carrier 50 to peel off the release layer 51 or by using other suitable processes to remove the temporary carrier 50. A cleaning process is optionally performed on the bottom surface 110 b of the first redistribution structure 110 to remove the residue of the release layer 51. In some embodiments, a surface finishing process is performed on the terminal bonding pads BP2 at the topmost level of the coarse conductive pattern CP of the second redistribution structure 140 and/or the chip bonding pads BP1 at the bottom surface 110 b of the first redistribution structure 110 to form the surface finishing layers 150 thereon for protection and/or solderability. The manufacturing process of an interposer IP1 is then substantially complete.

FIG. 2 is a schematic cross-sectional view illustrating an assembly including an interposer according to some embodiments of the invention. Referring to FIG. 2, an assembly AS1 includes the interposer IP1, a semiconductor chip 10 disposed on and electrically connected to the first redistribution structure 110, and a plurality of external terminals 20 disposed on the second redistribution structure 140 and opposite to the semiconductor chip 10.

The semiconductor chip 10 may be connected to the bottom surface 110 b of the first redistribution structure 110 using, for example, the flip-chip bonding. For example, the conductive bumps 12 of the semiconductor chip 10 are boned to the chip bonding pads BP1 of the first redistribution structure 110. In some embodiments, an underfill 30 may be formed on the bottom surface 110 b of the first redistribution structure 110 to fill the gap between the bottom surface 110 b and the semiconductor chip 10 so as to enhance the reliability of the flip-chip bonding. In some embodiments, more than one semiconductor chips 10, which perform the same or different functions, can be disposed on the interposer IP1. In such case, multiple semiconductor chips 10 may be electrically connected to each other through the interposer IP1. The amount of the semiconductor chips 10 disposed on the interposer IP1 construes no limitation in the disclosure. In certain embodiments in which the active device 120 of the interposer IP1 includes router circuits disposed therein, the electrical signal from one of the semiconductor chip 10 are routed through the active device 120 to another one of the semiconductor chip 10. The active device 120 in the interposer IP1 may be disposed proximal to the semiconductor chips 10 so as to provide a short signal transmitting path, thereby achieving better electrical performance.

The external terminals 20 may be electrically coupled to the semiconductor chip 10 through the interposer IP1. For example, the external terminals 20 are solder balls, and may be formed using a ball placement process to place on the terminal bonding pads BP2 of the second redistribution structure 140. A soldering process and a reflowing process are optionally performed to enhance the adhesion between the external terminals 20 and the terminal bonding pads BP2 of the second redistribution structure 140. In some embodiments, the assembly AS1 is further disposed on a circuit carrier (e.g., printed circuit board (PCB), a system board, a mother board, or the like). For example, the external terminals 20 are disposed on the circuit carrier to electrically connect the assembly AS1 to other elements on/in the circuit carrier.

FIG. 3A and FIG. 3B are schematic cross-sectional views illustrating a manufacturing method of an assembly including an interposer according to some embodiments of the invention. The identical or similar numbers refer to the identical or similar elements throughout the drawings, and detail thereof is not repeated. Referring to FIG. 3A, an interposer IP2 is formed on the temporary carrier 50. The interposer IP2 includes the first redistribution structure 110 formed over the temporary carrier 50, at least one active device 220 disposed on and electrically connected to the first redistribution structure 110, an intermediate dielectric layer 230 formed on the first redistribution structure 110 and encapsulating the active device 220, at least one conductive through via TV formed on the first redistribution structure 110 and extending through the intermediate dielectric layer 230, a third redistribution structure 210 formed on the intermediate dielectric layer 230 and the conductive through via TV to electrically coupled to the first redistribution structure 110 through the conductive through via TV, and the second redistribution structure 140 formed on and electrically connected to the third redistribution structure 210.

The active device 220 may be the same or similar types of device to the active device 120. In some embodiments, the active device 220 may be or may include bumpless chip(s). For example, the active surface 220 a of the active device 220 is free of conductive terminals. The active surface 220 a of the active device 220 may be connected to the fine conductive pattern FP of the first redistribution structure 110 through metal-to-metal bonding (e.g., direct copper-to-copper bonding), hybrid bonding, or other suitable electrical coupling techniques. In some embodiments, the bonding interface between the active surface 220 a of the active device 220 and the fine conductive pattern FP of the first redistribution structure 110 is free of solder material. Since the active surface 220 a of the active device 220 is directly connected to the fine conductive pattern FP of the first redistribution structure 110 at the top surface 110 t, a signal length therebetween may be shorten.

The material of the intermediate dielectric layer 230 may be similar to that of the intermediate dielectric layer 130. The conductive through via TV is laterally covered by the intermediate dielectric layer 230, and physically and electrically connected to the fine conductive pattern FP of the first redistribution structure 110 at the top surface 110 t. In some embodiments, after forming the first redistribution structure 110, the conductive through via TV is formed on the fine conductive pattern FP of the first redistribution structure 110 by forming of a patterned photoresist (not shown) on the first redistribution structure 110 as a mask, plating conductive materials inside the openings (not shown) of the patterned photoresist, and stripping the patterned photoresist. It should be noted that the number of conductive through via TV illustrated in FIG. 3A is merely exemplary, multiple conductive through vias TV or single conductive through via TV are possible. After forming the conductive through via TV, the active device 220 is disposed on the first redistribution structure 110 and aside the conductive through via TV. In some embodiments, the active device 220 is surrounded by the conductive through vias TV. After disposing the active device 220, the dielectric material is formed on the first redistribution structure 110 to encapsulate the conductive through via TV and the active device 220 to form the intermediate dielectric layer 230. In some embodiments, a planarization process (e.g., a grinding process, a chemical-mechanical polish process, an etching, etc.) is optionally performed on the conductive through via TV and the intermediate dielectric layer 230, such that the top surfaces TVt of the conductive through vias TV and the top surface 230 t of the intermediate dielectric layer 230 are substantially coplanar.

In other embodiments, the intermediate dielectric layer 230 is formed on the first redistribution structure 110 to cover the active device 220, then a portion of the intermediate dielectric layer 230 is removed to form through hole (not shown) exposing the underlying fine conductive pattern FP, and subsequently, the conductive material is formed inside the through hole of the intermediate dielectric layer 230 so as to form the conductive through via TV. The conductive through via TV may be or may include copper pillars or other suitable metallic pillars. Other forms and shapes of the conductive through via TV may be used. It should be noted that other processes may be used to form the conductive through via TV and the intermediate dielectric layer 230, which is not limited thereto. In some embodiments, the height of the conductive through via TV is greater than the thickness of the active device 220. In other embodiments, the conductive through via TV may be thinned to have a similar height as the active device 220, and the intermediate dielectric layer 230 may or may not cover the rear surface 220 r of the active device 220.

Continue to FIG. 3A, after forming the conductive through via TV and the intermediate dielectric layer 230, the third redistribution structure 210 is formed on the top surfaces TVt of the conductive through vias TV and the top surface 230 t of the intermediate dielectric layer 230. Materials and the forming process of the third redistribution structure 210 may be similar to those of the first redistribution structure 110. For example, the third redistribution structure 210 includes the fine conductive pattern FP′ physically and electrically connected to the underlying conductive through via TV and overlying conductive features (e.g., fine conductive via FV′ or coarse conductive pattern CP of the second redistribution structure 140), a fine dielectric layer FD′ formed on the intermediate dielectric layer 230 and partially covering the fine conductive pattern FP′, and the fine conductive via FV′ laterally covered by the fine dielectric layer FD′ and interconnecting the fine conductive pattern FP′ in different levels or interconnecting between the fine conductive pattern FP′ and the overlying coarse conductive pattern CP of the second redistribution structure 140. The fine conductive pattern FP′ may meet the fine-pitched requirements of the underlying conductive through vias TV. It should be noted that the illustration of the third redistribution structure 210 in FIG. 3A is merely exemplary, the third redistribution structure 210 may be formed as a multi-layered structure. In some embodiments, a fan-out wafer level packaging (FOWLP) technique is used to form the third redistribution structure 210 and the underlying structure. In some embodiments, the third redistribution structure 210 is pre-formed, and after forming the intermediate dielectric layer 230 and the conductive through vias TV, the third redistribution structure 210 is transferred to be disposed on the intermediate dielectric layer 230 and electrically connected to the conductive through vias TV.

Still referring to FIG. 3A, the second redistribution structure 140 is formed on the third redistribution structure 210. For example, the coarse dielectric layer CD of the second redistribution structure 140 is formed on the fine dielectric layer FD′ of the third redistribution structure 210. The coarse dielectric layer CD may include a plurality of openings (not shown) exposing the underlying fine conductive pattern FP′ for further electrical connection. The coarse conductive via CV of the second redistribution structure 140 may be formed in the openings of the coarse dielectric layer CD to be physically and electrically connected to the underlying fine conductive pattern FP′ of the third redistribution structure 210. The coarse conductive pattern CP may stack on the coarse dielectric layer CD, and may be formed on and electrically connected to the coarse conductive via CV. In some embodiments, the conductive structure interconnected in the first redistribution structure 110, the intermediate dielectric layer 130, the third redistribution structure, and the second redistribution structure 140 is free of solder material connected therebetween.

In some embodiments, the dimensions of the coarse conductive via CV and the coarse conductive pattern CP of the second redistribution structure 140 are respectively greater than those of the fine conductive via FV′ and the fine conductive pattern FP′ of the third redistribution structure 210. In some embodiments, the coarse conductive via CV, the fine conductive vias FV and FV′ are tapered towards the same direction, such as towards the temporary carrier 50. The thickness of the fine dielectric layer FD′ of the third redistribution structure 210 may be thinner than the thickness of the coarse dielectric layer CD of the second redistribution structure 140. The thickness of the intermediate dielectric layer 230 may be thicker than the thickness of the fine dielectric layer FD′ of the third redistribution structure 210.

In some embodiments, the first redistribution structure 110 and the third redistribution structure 210 are fabricated according to IC design rule, and the wiring (e.g., the fine conductive patterns FP and FP′, the fine conductive vias FV and FV′) are formed in fine pitch. The second redistribution structure 140 may be fabricated according to PCB design rule, and the wiring (e.g., the coarse conductive pattern CP, the coarse conductive vias CV) are formed in a larger scale compared to the wiring in the first redistribution structure 110 and the third redistribution structure 210. The line/spacing (L/S) of the fine conductive pattern FP of the first redistribution structure 110 and/or the fine conductive pattern FP′ of the third redistribution structure 210 may be finer than that of the coarse conductive pattern CP of the second redistribution structure 140.

Referring to FIG. 3B, an assembly AS2 includes the interposer IP2 is provided. For example, after forming the interposer IP2, the temporary carrier 50 is removed. The surface finishing layer (not shown) may be formed on the chip bonding pads of the first redistribution structure 110 and/or the terminal boning pas of the second redistribution structure 140. The semiconductor chip(s) 10 may be disposed on the bottom surface 110 b of the first redistribution structure 110 as described in FIG. 2, so the detailed descriptions are not repeated herein. In some embodiments, the external terminals 20 are disposed on the outermost level of the coarse conductive pattern CP of the second redistribution structure 140 and opposite to the semiconductor chip 10. Alternatively, the external terminals 20 are omitted, and the second redistribution structure 140 of the interposer IP2 may be bonded to other components or packages, and thus the external terminals 20 are illustrated in dashed lines.

FIG. 4 is a schematic cross-sectional view illustrating an assembly including an interposer according to some embodiments of the invention. Referring to FIG. 4, an assembly AS3 is provided. The assembly AS3 is similar to the assembly AS2 shown in FIG. 3 and the difference therebetween lies in the active device 120 of the interposer IP3. For example, the conductive terminals 122 of the active device 120 are physically and electrically connected to the fine conductive pattern FP of the first redistribution structure 110. The active device 120 in the present embodiment is similar to the active device 120 described in FIG. 1B, so the detailed descriptions are not repeated herein.

FIG. 5 is a schematic cross-sectional view illustrating an assembly including an interposer according to some embodiments of the invention. Referring to FIG. 5, an assembly AS4 is provided. The assembly AS4 is similar to the assembly AS2 shown in FIG. 3 and the difference therebetween lies in the active device 320 of the interposer IP4. For example, the active device 320 includes a semiconductor substrate 322 having the active surface 320 a and the rear surface 320 r opposite to each other, a plurality of conductive terminals 322 distributed at the active surface 320 a to be physically and electrically connected to the fine conductive pattern FP of the first redistribution structure 110, and a plurality of through semiconductor vias TSV penetrating through the semiconductor substrate 322. In some embodiments, the semiconductor substrate 322 is made of silicon, and the through semiconductor vias TSV are referred to as through silicon vias. The through semiconductor vias TSV are formed to provide a conductive path oriented between the active surface 320 a and the rear surface 320 r. In some embodiments, the through semiconductor vias TSV are tapered from the rear surface 320 r to the active surface 320 a. Alternatively, the through semiconductor vias TSV are tapered from the active surface 320 a to the rear surface 320 r or the through semiconductor vias TSV have substantially vertical sidewalls.

In some embodiments, conductive features CF may be formed on the rear surface 320 r of the semiconductor substrate 322 to be physically and electrically connected to the through semiconductor vias TSV and the fine conductive pattern FP′ of the third redistribution structure 210. In some embodiments, the surfaces of the conductive features CF and the top surfaces TVt of the conductive through vias TV are substantially coplanar. In some embodiments, the conductive features CF are omitted.

Further to that described above, the interposer includes the first redistribution structure having the fine conductive pattern that can meet the requirements of high bump density of the semiconductor chips and the active device. The interposer includes the second redistribution structure having the coarser conductive pattern at the opposite side of the first redistribution structure for connecting the external terminals. In addition, the interposer includes the active device embedded therein for communicating the semiconductor chips disposed on the interposer. Since the active device may take up significant space on the semiconductor chips, by disposing the active device inside the interposer may release the space for semiconductor chips, thereby saving space on the semiconductor chips. Moreover, the interposer may include various functions by embedding designed active device(s) therein. Furthermore, the active device is buried at the side of the interposer proximal to the semiconductor chips, which may keep a short signal length in order to minimize a noise between operations and to improve a signal performance.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. 

What is claimed is:
 1. A manufacturing method of an interposer for disposing a semiconductor chip and an external terminal at two opposing sides, comprising: bonding an active device to a first redistribution structure, wherein an active surface of the active device is in electrical contact with the first redistribution structure; forming a dielectric layer on the first redistribution structure to encapsulate the active device; and forming a second redistribution structure over the dielectric layer to be electrically coupled to the first redistribution structure, wherein the first conductive pattern of the first redistribution structure is formed according to a first design rule to be finer than a second conductive pattern of the second redistribution structure formed according to a second design rule, the semiconductor chip and the external terminal are configured to be respectively disposed on the first conductive pattern and the second conductive pattern.
 2. The manufacturing method of claim 1, wherein the second redistribution structure is formed by a build-up process.
 3. The manufacturing method of claim 1, further comprising: removing a portion of the dielectric layer aside the active device to form a through hole exposing at least a portion of the first conductive pattern of the first redistribution structure, and forming a conductive material in the through hole to be in contact with the first conductive pattern of the first redistribution structure.
 4. The manufacturing method of claim 3, wherein the through hole is tapered towards the first redistribution structure, the conductive material is formed inside the through hole and on a top surface of the dielectric layer, and then the conductive material on the top surface of the dielectric layer is patterned to form the second conductive pattern of the second redistribution structure.
 5. The manufacturing method of claim 3, wherein the conductive material is formed inside the through hole to form a conductive through via, and then a third redistribution structure is formed on the conductive through via and the dielectric layer and a third conductive pattern of the third redistribution structure is formed according to the first design rule.
 6. The manufacturing method of claim 5, wherein the active device is provided with a through semiconductor via formed therein, and a conductive connector is formed on a rear surface of the active device to connect the through semiconductor via.
 7. The manufacturing method of claim 6, wherein before forming the third redistribution structure, a planarization process is performed on the conductive through via and the conductive connector.
 8. The manufacturing method of claim 1, wherein the active device is bonded to the first conductive pattern of the first redistribution structure using a flip-chip process.
 9. The manufacturing method of claim 1, wherein the active device is bonded to the first conductive pattern of the first redistribution structure using a direct copper-to-copper bonding process.
 10. The manufacturing method of claim 1, further comprising: forming the first redistribution structure on a temporary carrier; and de-bonding the temporary carrier after forming the second redistribution structure to expose the first conductive pattern, and then bonding the semiconductor chip to a bond pad of the first conductive pattern of the first redistribution structure. 